/**
 ******************************************************************************
 * @file    pad.h
 * @author  hyseim software Team
 * @date    26-Mar-2024
 * @brief   
 ******************************************************************************
 * @attention
 * 
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 * 
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 * 
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __PAD_H__
#define __PAD_H__

#ifdef __cplusplus
 extern "C"{
#endif

/* Includes ------------------------------------------------------------------*/
#include "utils.h"
/** @addtogroup IM110GW_StdPeriph_Driver
  * @{
  */

/** @addtogroup PAD
  * @{
  */

#define PAD_NUM 124
#define XIO_NUM 110

typedef struct 
{
    __IO uint32_t PAD[PAD_NUM]; 
}PADFunc_Typedef;

typedef struct
{
    __IO uint32_t XIO[XIO_NUM];
} IOFunc_TypeDef;

typedef struct
{
    struct
    {
             uint32_t RESERVED0[4];
        __IO uint32_t CS;
        __IO uint32_t OS;
        __IO uint32_t OD;
        __IO uint32_t PU;
        __IO uint32_t PD;
        __IO uint32_t DR;
        __IO uint32_t SR;
             uint32_t RESERVED1[5];
    }PAD[32]; 
} PADCfg_TypeDef;

#define PADFUNC                 ((PADFunc_Typedef *)    (GPIOTOP_BASE + 0x0000))
#define IOFUNC                  ((IOFunc_TypeDef  *)    (GPIOTOP_BASE + 0x0200))

#define PADA                    ((PADCfg_TypeDef *)    (GPIOAO_BASE + 0x0000))
#define PADB                    ((PADCfg_TypeDef *)    (GPIOAO_BASE + 0x1000))
#define PADC                    ((PADCfg_TypeDef *)    (GPIOAO_BASE + 0x2000))
#define PADD                    ((PADCfg_TypeDef *)    (GPIOAO_BASE + 0x3000))

typedef enum
{
    GPIOA0_MTIC5V_TRGMUXOUT7_XIO0,
    GPIOA1_MTIC5U_TRGMUXOUT6_XIO1,
    GPIOA2_MTIC5W_TRGMUXOUT2_XIO2,
    GPIOA3_MTIOC0A_TRGMUXOUT1_XIO3,
    GPIOA4_MTIOC0B_TRGMUXOUT5_XIO4,
    GPIOA5_MTIOC0C_TRGMUXOUT4_XIO5,
    GPIOA6_MTIOC0D_XIO6,
    GPIOA7_MTIOC1A_XIO7,
    GPIOA8_MTIOC1B_XIO8,
    GPIOA9_MTIOC2A_XIO9,
    GPIOA10_MTIOC2B_XIO10,
    GPIOA11_MTIOC6A_XIO11,
    GPIOA12_MTIOC6B_TRGMUXIN6_XIO12,
    GPIOA13_MTIOC6C_XIO13,
    GPIOA14_MTIOC6D_XIO14,
    GPIOA15_MTIOC7A_XIO15,
    GPIOA16_MTIOC7B_XIO16,
    GPIOA17_MTIOC7C_XIO17,
    GPIOA18_MTIOC7D_XIO18,
    GPIOA19_MTIOC4A_XIO19,
    GPIOA20_MTIOC4B_XIO20,
    GPIOA21_MTIOC4C_XIO21,
    GPIOA22_MTIOC4D_XIO22,
    GPIOA23_MTIOC3A_XIO23,
    GPIOA24_MTIOC3B_XIO24,
    GPIOA25_XIO25_ADC0_SE16,
    GPIOA26_XIO26_ADC0_SE17,
    GPIOA27_XIO27_ADC0_SE18,
    GPIOA28_MTIOC3C_XIO28_CMP_IN3,
    GPIOA29_MTIOC3D_TRGMUXIN0_XIO29,
    GPIOA30_TRGMUXIN1_XIO30,
    GPIOA31_XIO31_ADC0_SE11_CMP_IN4,
    GPIOB0_XIO32_ADC0_SE10_CMP_IN5,
    GPIOB1_MTCLKA_XIO33_CMP_IN6,
    GPIOB2_MTCLKB_XIO34_CMP_IN7,
    GPIOB3_MTCLKC_TRGMUXIN7_XIO35,
    GPIOB4_MTCLKD_XIO36,
    GPIOB5_XIO37,
    GPIOB6_XIO38,
    GPIOB7_XIO39_ADC0_SE9,
    GPIOB8_XIO40_ADC0_SE8,
    GPIOB9_XIO41,
    GPIOB10_XIO42,
    GPIOB11_XIO43_ADC0_SE15,
    GPIOB12_XIO44_ADC0_SE14,
    GPIOB13_XIO45_ADC0_SE19,
    GPIOB14_TRGMUXIN8_XIO46_ADC0_SE13,
    GPIOB15_XIO47_ADC0_SE20,
    GPIOB16_TRGMUXIN9_XIO48_ADC0_SE12,
    GPIOB17_XIO49_ADC0_SE21,
    GPIOB18_TRGMUXIN2_XIO50_ADC0_SE7,
    GPIOB19_XIO51_ADC0_SE22,
    GPIOB20_XIO52_ADC0_SE23,
    GPIOB21_TRGMUXIN3_XIO53_ADC0_SE6,
    GPIOB22_XIO54,
    GPIOB23_XIO55,
    GPIOB24_XIO56,
    GPIOB25_XIO57,
    GPIOB26_TRGMUXIN10_XIO58,
    GPIOB27_TRGMUXIN11_XIO59,
    GPIOB28_XIO60,
    GPIOB29_XIO61,
    GPIOB30_XIO62_ADC0_SE5_ADC1_SE15,
    GPIOB31_XIO63_ADC0_SE4_ADC1_SE14,
    GPIOC0_XIO64,
    GPIOC1_XIO65,
    GPIOC2_XIO66,
    GPIOC3_XIO67,
    GPIOC4_XIO68_ADC0_SE3,
    GPIOC5_XIO69,
    GPIOC6_XIO70_ADC0_SE2,
    GPIOC7_XIO71,
    GPIOC8_XIO72,
    GPIOC9_XIO73_ADC1_SE16,
    GPIOC10_XIO74_ADC1_SE17,
    GPIOC11_XIO75,
    GPIOC12_XIO76,
    GPIOC13_XIO77_ADC1_SE15,
    GPIOC14_XIO78_ADC1_SE14,
    GPIOC15_XIO79_ADC0_SE9_ADC1_SE9,
    GPIOC16_XIO80_ADC0_SE8_ADC1_SE8,
    GPIOC17_XIO81_ADC1_SE7,
    GPIOC18_XIO82_ADC1_SE18,
    GPIOC19_XIO83_ADC1_SE6,
    GPIOC20_TRGMUXIN4_XIO84_ADC1_SE3,
    GPIOC21_TRGMUXIN5_XIO85_ADC1_SE2,
    GPIOC22_XIO86_ADC1_SE19,
    GPIOC23_XIO87_ADC1_SE1,
    GPIOC24_XIO88_ADC1_SE0,
    GPIOC25_XIO89_ADC1_SE20,
    GPIOC26_XIO90,
    GPIOC27_XIO91,
    GPIOC28_XIO92,
    GPIOC29_XIO93_ADC1_SE21,
    GPIOC30_XIO94,
    GPIOC31_XIO95_ADC1_SE22,
    GPIOD0_TRGMUXOUT0_XIO96_ADC0_SE1_CMP_IN1,
    GPIOD1_XIO97_ADC1_SE23,
    GPIOD2_TRGMUXOUT3_XIO98_ADC0_SE0_CMP_IN0,
    GPIOD3_XIO99,
    GPIOD4_XIO100_ADC1_SE5,
    GPIOD5_XIO101_ADC1_SE4,
    GPIOD6_XIO102_ADC1_SE13,
    GPIOD7_XIO103_ADC1_SE12,
    GPIOD8_XIO104_ADC1_SE11,
    GPIOD9_XIO105_ADC1_SE10,
    GPIOD10_LUARTTX_XIO106,
    GPIOD11_LUARTRX_XIO107,
    GPIOD12_XIO108,
    GPIOD13_XIO109,
    GPIOD14_XIO110,
    GPIOD15_XIO111,
    GPIOD16_XIO112,
    GPIOD17_SPIBCLK_XIO113,
    GPIOD18_SPIBCS_XIO114,
    GPIOD19_SPIBDI_XIO115,
    GPIOD20_SPIBDO_XIO116,
    GPIOD21_JTAGTDO_XIO117,
    GPIOD22_XIO118,
    GPIOD23_XIO119,
    GPIOD24_JTAGTDI_XIO120,
    GPIOD25_JTAGTCK_XIO121_CMP_IN2,
    GPIOD26_JTAGTMS_XIO122,
    GPIOD27_PMUDEBUGO_XIO123,
    GPIOD28_XIO124
} PADName;

typedef enum
{
    XIO_ASSI0_IO0,
    XIO_ASSI0_IO1,
    XIO_ASSI0_IO2,
    XIO_ASSI0_IO3,
    XIO_ASSI1_IO0,
    XIO_ASSI1_IO1,
    XIO_ASSI1_IO2,
    XIO_ASSI1_IO3,
    XIO_ASSI2_IO0,
    XIO_ASSI2_IO1,
    XIO_ASSI2_IO2,
    XIO_ASSI2_IO3,
    XIO_ASSI3_IO0,
    XIO_ASSI3_IO1,
    XIO_ASSI3_IO2,
    XIO_ASSI3_IO3,
    XIO_ASSI4_IO0,
    XIO_ASSI4_IO1,
    XIO_ASSI4_IO2,
    XIO_ASSI4_IO3,
    XIO_ASSI5_IO0,
    XIO_ASSI5_IO1,
    XIO_ASSI5_IO2,
    XIO_ASSI5_IO3,
    XIO_ASSI6_IO0,
    XIO_ASSI6_IO1,
    XIO_ASSI6_IO2,
    XIO_ASSI6_IO3,
    XIO_ASSI7_IO0,
    XIO_ASSI7_IO1,
    XIO_ASSI7_IO2,
    XIO_ASSI7_IO3,
    CAN0_RX,
    CAN0_TX,
    CAN0_STBY,
    CAN1_RX,
    CAN1_TX,
    CAN1_STBY,
    CAN2_RX,
    CAN2_TX,
    CAN2_STBY,
    I2S_SDIO1,
    I2S_SDIO0,
    I2S_WS,
    I2S_SCK,
    I2S_MCLK,
    IRQ0,
    IRQ1,
    WDTOVF,
    NMI,
    POE0_N,
    POE4_N,
    POE8_N,
    ADTRG0N,
    ADTRG1N,
    RTCCLK,
    QEI0A,
    QEI0B,
    QEI0IDX,
    QEI0UPDN,
    TRACE_TX,
    CLK_FAIL,
    MTIC5V,
    MTIC5U,
    MTIC5W,
    MTIOC0A,
    MTIOC0B,
    MTIOC0C,
    MTIOC0D,
    MTIOC1A,
    MTIOC1B,
    MTCLKA,
    MTCLKB,
    MTIOC2A,
    MTIOC2B,
    MTIOC6A,
    MTIOC6B,
    MTIOC6C,
    MTIOC6D,
    MTIOC7A,
    MTIOC7B,
    MTIOC7C,
    MTIOC7D,
    MTIOC4A,
    MTIOC4B,
    MTIOC4C,
    MTIOC4D,
    MTIOC3A,
    MTIOC3B,
    MTIOC3C,
    MTIOC3D,
    MTCLKC,
    MTCLKD,
    EWM_I,
    EWM_O,
    LUART_TX,
    LUART_RX,
    QEI1A,
    QEI1B,
    QEI1IDX,
    QEI1UPDN,
    CMP_OUT,
    CLK_TEST,
    LVDT,
    LPSPI_IO0,
    LPSPI_IO1,
    LPSPI_IO2,
    LPSPI_IO3,
    LPI2C_SDA,
    LPI2C_SCL,
} XIOFuncSel;

typedef enum
{
    PAD_Pin_0,
    PAD_Pin_1,
    PAD_Pin_2,
    PAD_Pin_3,
    PAD_Pin_4,
    PAD_Pin_5,
    PAD_Pin_6,
    PAD_Pin_7,
    PAD_Pin_8,
    PAD_Pin_9,
    PAD_Pin_10,
    PAD_Pin_11,
    PAD_Pin_12,
    PAD_Pin_13,
    PAD_Pin_14,
    PAD_Pin_15,
    PAD_Pin_16,
    PAD_Pin_17,
    PAD_Pin_18,
    PAD_Pin_19,
    PAD_Pin_20,
    PAD_Pin_21,
    PAD_Pin_22,
    PAD_Pin_23,
    PAD_Pin_24,
    PAD_Pin_25,
    PAD_Pin_26,
    PAD_Pin_27,
    PAD_Pin_28,
    PAD_Pin_29,
    PAD_Pin_30,
    PAD_Pin_31,
} PAD_Pin;

typedef enum
{
    PADFUNC0,
    PADFUNC1,
    PADFUNC2,
    PADFUNC3,
    PADFUNC4,
    PADFUNC5,
    PADFUNC6,
} PadFunc;

#define PAD_CMOSMODE_ENABLE     0x04
#define PAD_OS_ENABLE           0x05
#define PAD_OD_ENABLE           0x06
#define PAD_PU_ENABLE           0x07
#define PAD_PD_ENABLE           0x08
#define PAD_DR_ENABLE           0x09
#define PAD_SR_ENABLE           0x0A


#define PAD_IMODE_CMOS          (1<<PAD_CMOSMODE_ENABLE)    /* defalt is Schmitt trigger input buffer mode*/
#define PAD_OTYPE_OS            (1<<PAD_OS_ENABLE)
#define PAD_OTYPE_OD            (1<<PAD_OD_ENABLE)
#define PAD_PUPD_PULLUP         (1<<PAD_PU_ENABLE)
#define PAD_PUPD_PULLDOWN       (1<<PAD_PD_ENABLE)
#define PAD_DRIVE_LOW           (1<<PAD_DR_ENABLE)          /* default is high drive strength */
#define PAD_SLEWRATE_SLOW       (1<<PAD_SR_ENABLE)          /* default is fast slew strength */
#define PAD_DEFAULT_CONFIG      0x00000000U

void PAD_Init(PADCfg_TypeDef *pad, PAD_Pin pin, uint32_t padConfig);
void PAD_SelFunc(PADName PadName, PadFunc padFunc);
void PAD_XIOMUX(PADName PadName, XIOFuncSel ioFunc);

#ifdef __cplusplus
}
#endif
#endif  /* __PAD_H__ */